In some Central Processing Unit (“CPU”) system architectures, especially those used in battery-powered systems, hardware mechanisms control power-saving modes of the CPU. The Advanced Configuration and Power interface (“ACPI”) Specification is an open standard for unified operating system-centric device configuration and power management. While the context of the present application is not limited to ACPI, it provides some definitions which are useful for understanding the power modes of industry standard CPU's.
The ACPI defines various CPU power states (“C-states”) of increasing power savings (decreasing power consumption) and, usually, with corresponding increasing latency. These latencies, as known in the art, include the time required to enter and/or exit a level of a power saving mode. In general, mobile computing systems attempt to conserve power by placing the processor in a lower-power C-state when there are no instructions to be executed. The ACPI defines a mechanism for notifying Operating System (“OS”) software of the C-state capabilities and latencies of a CPU thread, core, and package based on CPU identity mechanisms that are known in the art and, in the ACPI, the OS software manages the C-state capabilities of the processor.
Conventional processor designs prevent entry into a power managed state when the transition rate is high (for example, due to a high interrupt rate). Since the performance impact of entry into the power managed state cannot be known at runtime, designs are calibrated to avoid power management usage when the expected transition rate is less than the “typical” entry delay or when the residency in a specific low-power state is short (making entry into the low-power state inefficient). The low-power state is efficient only if its residency is sufficiently long so as the power savings associated with the low-power state is greater than the power consumed during the entry and exit transitions (to and from the low-power state). However, where transition delays are not uniform, the conventional approach is not effective, particularly multi-core processors that have shared resources, such as caches.